// phase_seq.sv — cycles A -> B -> C -> A while 'go' is high
module phase_seq (
  input  logic       clk, rst, go,
  output logic [1:0] phase
);
  localparam logic [1:0] A = 2'd0, B = 2'd1, C = 2'd2;   // 2'd3 is never used

  always_ff @(posedge clk) begin
    if (rst)     phase <= A;
    else if (go) case (phase)
                   A:       phase <= B;
                   B:       phase <= C;
                   default: phase <= A;   // C (and the unused 3) go back to A
                 endcase
  end
endmodule