// adder_seq_eq.sv — sequential equivalence miter
module adder_seq_eq (
  input logic       clk, rst,
  input logic [7:0] a, b
);
  logic [8:0] sum_ref, sum_imp;
  adder_reg_out u_ref (.clk, .rst, .a, .b, .sum(sum_ref));
  adder_reg_in  u_imp (.clk, .rst, .a, .b, .sum(sum_imp));

  initial assume (rst);
  a_seq_equiv: assert property (@(posedge clk) disable iff (rst) sum_ref == sum_imp);
endmodule