// prio_enc_v1.sv — original: explicit casez
module prio_enc_v1 (
  input  logic [7:0] req,
  output logic [2:0] idx,     // index of the LOWEST set bit
  output logic       any
);
  always_comb begin
    casez (req)
      8'b???????1: idx = 3'd0;
      8'b??????10: idx = 3'd1;
      8'b?????100: idx = 3'd2;
      8'b????1000: idx = 3'd3;
      8'b???10000: idx = 3'd4;
      8'b??100000: idx = 3'd5;
      8'b?1000000: idx = 3'd6;
      8'b10000000: idx = 3'd7;
      default:     idx = 3'd0;
    endcase
  end
  assign any = |req;
endmodule