// gray_counter.sv
module gray_counter #(
  parameter int W = 4
) (
  input  logic         clk, rst, en,
  output logic [W-1:0] gray
);
  logic [W-1:0] bin;
  always_ff @(posedge clk)
    if (rst)     bin <= '0;
    else if (en) bin <= bin + 1'b1;
  assign gray = bin ^ (bin >> 1);
endmodule